Block - Level Prediction for Wide - Issue Superscalar Processors

Changes in control ow, caused primarily by conditional branches, are a prime impediment to the performance of wide-issue superscalar processors. This paper investigates a block-level prediction scheme to mitigate the e ects of control ow changes caused by conditional branches. Instead of predicting the outcome of each conditional branch individually, this scheme predicts the target of a sequential block of instructions, thereby allowing the superscalar processor to go past multiple branches per cycle. This approach is evaluated using the MIPS architecture, for 8-way and 12way superscalar processors, and an improvement in e ective fetch size of approximately 15% and 25%, respectively, over identical processors that use branch prediction is observed. No appreciable di erence in the prediction accuracy was observed, although blocklevel prediction predicted one out of four outcomes.